The present invention relates to a method for fabricating MOS (Metal Oxide Semiconductor) semiconductor devices such as insulated-gate transistors to be formed on an insulating material or silicon wafer or the like. In particular, the invention relates to a semiconductor device fabrication method applicable to thin film transistors to be formed on a-glass substrate having a glass transition point of 750.degree. C. or lower.
Conventionally, MOS semiconductor devices have been used for various kinds of electronic devices or the like, a typical example thereof being MOS transistors (also called MOSFET, insulated gate transistors, etc.). Among electronic devices, in particular, thin film transistors (hereinafter, referred to as TFT) widely used as semiconductor devices for driving active matrix type liquid crystal displays, image sensors and the like can be included in the MOS semiconductor devices, in the wide sense, because of their being partly similar in structure to the MOS transistors.
Particularly in recent years, in keeping up with increasing demands for scaling down and higher speed of semiconductor devices, polysilicon TFTs using polysilicon thin film having a higher electron field-effect mobility have been developed instead of amorphous silicon TFTs using amorphous silicon thin film as the active layer.
However, it is pointed out as a drawback that, in general, using the polysilicon thin film as the active layer of a MOS transistor would result in lower breakdown voltage of drain junction as well as increased junction leak current (hereinafter, referred to as OFF-state current). It is also known that forming an off-set gate structure or LDD (Lightly Doped Drain) structure is effective for breakdown voltage enhancement and OFF-state current reduction of MOS transistors.
The off-set gate structure is a structure in which an end portion of the gate electrode is shifted toward the channel region rather than the boundary portion between the channel region and the source/drain region, which is a heavily doped region so that a non-doped region with no dopants introduced thereto is provided between the end portion of the gate electrode and the source/drain region.
The LDD structure is a structure in which a lightly doped region of the same conductive type as the source/drain region is formed in at least one boundary portion between the channel region and the source/drain region that is a highly doped region. This lightly doped region is called LDD region. One example of the LDD structure in shown in FIG. 7.
Hitherto, such LDD structure as described above has been widely used for many MOS semiconductor devices including MOS transistors. Forming the LDD region or non-doped region causes a gentle dopant level profile to be formed between the channel region and the source/drain region, while separation of the gate electrode end and the source/drain region end from each other causes the OFF-state current to be reduced and the electric field in proximity to the source/drain region to be relaxed.
Nonetheless, as transistors go progressively smaller-sized with the LDD region resultantly smaller, the field relaxation effect reduces. As a result, a phenomenon has been pointed out as an issue that a high electric field is generated near the drain region and hot carriers thereby generated are trapped into the gate insulator on the LDD region, resulting in considerable fluctuations or reductions in device characteristics such as threshold voltage.
Thus, for improvement in the resistance to hot carriers, recent years' attention have been directed to the gate overlapped structure (hereinafter, referred to as GOLD structure) in which the gate electrode is overlapped with the LDD region via the gate insulator.
As to GOLD structures, various kinds of fabrication methods are conventionally proposed in, for example, Japanese Patent Laid-Open Publications HEI 6-13407, HEI 6-260646, HEI 8-153875, HEI 8-222736, HEI 9-45930 and the like.
First, Japanese Patent Laid-Open Publication HEI 9-45930 discloses a method for fabricating a GOLD structure by using a dopant blocking film made of photoresist. Japanese Patent Laid-Open Publication HEI 8-153875 discloses a method for fabricating a GOLD structure by using a conductive coating made primarily of silicon and formed on a side face of the gate electrode. Further, Japanese Patent Laid-Open Publications HEI 6-13407, HEI 6-260646 and HEI 8-222736 disclose methods for fabricating a GOLD structure by providing a second gate electrode which is made of conductive film and which connects with the gate electrode or covers the surface of the gate electrode.
As described above, the conventional LDD structures on one hand have remarkable effects for higher breakdown voltage and lowered OFF-state current of TFTs, and on the other hand have a problem that drive current (hereinafter, referred to as ON-state current) of TFTs lowers. In the conventional LDD structures, the LDD region is located outside the gate electrode. On this account, the LDD region is not subject to modulation by the gate voltage, causing the ON-state current to lower correspondingly. Particularly with the LDD region provided on the source region side, the ON-state current would lower to a large extent.
Meanwhile, according to the GOLD structure in which the gate electrode is overlapped with part of the LDD region via the gate insulator, since the LDD region is also modulated by the gate voltage, the OFF-state current can be reduced without lowering the ON-state current. Besides, deteriorations of device characteristics caused by hot carriers being trapped into the gate insulator, which have come up as an issue of the conventional LDD structures, can be prevented at the same time.
However, among the conventional fabrication methods for the GOLD structures as described above, in the fabrication method shown in Japanese Patent Laid-Open Publication HEI 9-45930, both the step of forming a lightly doped region which is the LDD region and the step of forming a heavily doped region which is the source and drain regions are implemented by using a dopant blocking film made of photoresist or the like. On this account, neither the lightly doped region nor the heavily doped region is formed in self alignment relative to the gate electrode, so that the positional alignment of these regions may be impaired. Further, the number of photolithography steps for forming the lightly doped region and the heavily doped region is increased by the exposure and development of the dopant blocking film and the like, making the fabrication method complex, which leads to an anxiety for effects on the conforming article rate and characteristic uniformity of TFTs.
In the fabrication method shown in Japanese Patent Laid-Open Publication HEI 8-153875, a side wall by conductive coating composed primarily of silicon is formed on the side face of the gate electrode.
Then the lightly doped region is formed in self alignment to the gate electrode, while the heavily doped region is formed in self alignment to the side wall. On this account, the level of overlap of the side wall with the lightly doped region cannot be set arbitrarily. Also, there arise needs for a film deposition step and an etchback step for forming the side wall. Because the setting and control of etching conditions for the etchback step is not easy, it can be foreseen that control of the width of the LDD region by arbitrarily setting the width of the side wall encounters difficulty.
Further, in the fabrication method shown in Japanese Patent Laid-Open Publication HEI 6-13407, a second gate electrode which connects with a first gate electrode is overlapped with the LDD region. In the fabrication method shown in Japanese Patent Laid-Open Publication HEI 6-260646, a second gate electrode is formed so as to cover the first gate electrode. In the fabrication method shown in Japanese Patent Laid-Open Publication HEI 8-22736, a second gate electrode which covers a first gate electrode is formed by selective CVD process. In these methods, the gate electrode becomes complex in structure, posing problems such as increases in step number and difficulties in setting and controlling film deposition conditions for forming the second gate electrode.
As shown above, according to the conventional fabrication methods for GOLD structure, it could be said that there are a number of problems, in all cases, such as increases in step number and involvement of some steps that could be hard to control, from the viewpoint of practical use, in particular, implementation of mass production.